By Jose Nazario
Failures of nano-metric applied sciences as a result of defects and shrinking strategy tolerances provide upward thrust to major demanding situations for IC checking out. because the version of primary parameters resembling channel size, threshold voltage, skinny oxide thickness and interconnect dimensions is going well past appropriate limits, new try methodologies and a deeper perception into the physics of defect-fault mappings are wanted. In Defect-Oriented trying out for Nano-Metric CMOS VLSI Circuits state-of-the-art of defect-oriented trying out is gifted from either a theoretical method in addition to from a realistic viewpoint. step by step dealing with of illness modeling, defect-oriented trying out, yield modeling and its utilization in universal economics practices permits deeper figuring out of concepts.
The development built during this e-book is vital to appreciate new attempt methodologies, algorithms and business practices. with no the perception into the physics of nano-metric applied sciences, it might be not easy to improve system-level try options that yield a excessive IC fault assurance. evidently, the paintings on defect-oriented checking out offered within the publication isn't ultimate, and it really is an evolving box with fascinating demanding situations imposed by way of the ever-changing nature of nano-metric applied sciences. try and layout practitioners from academia and will locate that Defect-Oriented checking out for Nano-Metric CMOS VLSI Circuits lays the principles for extra pioneering work.
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Additional info for Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits
2. 5 41 Delay Variation Model with ΔVt for Parallel Transistor Networks To predict the maximum delay variation caused in a CMOS gate by the Vt mismatch, the simple model shown in Figure 2-10 is used where K and α are constants of the technology and Cout models the output capacitance of the gate. The use of a Taylor expansion gives the following expression for the Δ T pLH = K ⋅ C out ⎡ α ⎢ W PMOS ⎢ (V DD − VTNOM ⎣ ) ( α + 1) ( Δ VT ) + α ( α + 1) (V DD − VTNOM ) (α + 2 ) ( Δ VT ) 2 ⎤ ⎥ ⎥⎦ delay variation of the gate.
Buelow, ‘‘IC Quality and Test Transparency,’’ Proceedings of the IEEE International Test Conference, pp. 295–301, 1988. 32. A. C. Miller, “IDDQ Testing in Deep Submicron Integrated Circuits,” Proceedings of the IEEE International Test Conference, pp. 724–729, 1999. 33. G. Moore, “Cramming More Components into Integrated Circuits,” Electronics, vol. 38, no. 8, Apr. 1965. 34. B. Mustafa Pulat, and L. M. Streb, ‘‘Position of Component Testing in Total Quality Management (TQM),’’ Proceedings of the IEEE International Test Conference, pp.
This awareness can lead to robust design practices such that the probabilities of many types of defects are reduced, or alternatively their detection is simplified. Similarly, test solutions for dominant types of defects may be generated to rationalize test costs. 16 Defect-oriented Testing for Nano-metric CMOS VLSI Circuits There are a number of defect types that may occur in a circuit and often different circuit types have to co-exist on the same die. Depending upon the circuit type (dynamic, static, digital, RAM, PLAs, or analog) defects influence the operation differently.