By Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
Advanced try out tools for SRAMs: powerful suggestions for Dynamic Fault Detection in Nanoscaled Technologies
Modern electronics will depend on nanoscaled applied sciences that current new demanding situations by way of checking out and prognosis. stories are fairly vulnerable to defects considering the fact that they take advantage of the know-how limits to get the top density. This publication is a useful consultant to the trying out and analysis of the most recent new release of SRAM, some of the most established form of thoughts. Classical equipment for trying out reminiscence are designed to deal with the so-called "static faults", yet those try out options should not enough for faults which are rising within the most up-to-date Very Deep Sub-Micron (VDSM) applied sciences. those new faults, often called "dynamic faults", aren't coated by means of classical algorithms and require the devoted try and prognosis suggestions provided during this book.
- First booklet to offer entire, cutting-edge insurance of dynamic fault checking out for SRAM memories;
- Presents content material utilizing a "bottom-up" process, from the examine of factors of malfunctions as much as the new release of shrewdpermanent attempt innovations;
- Includes case stories overlaying all reminiscence parts (core-cells, tackle decoders, write drivers, experience amplifiers, etc.);
- Proposes an exhaustive research of resistive-open defects in each one reminiscence part and the ensuing dynamic fault modeling.
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Extra info for Advanced Test Methods for SRAMs: Effective Solutions for Dynamic Fault Detection in Nanoscaled Technologies
6 where each point corresponds to a determined couple of values (clock cycle period, resistance value of defect Df4) and is placed in a certain area corresponding to a sensitization sequence like 1w0r0M , where M = 1–5. The graph in Fig. 6 can be read horizontally (by fixing a certain resistance value) and vertically (by fixing a certain clock cycle period). In the first case, for a certain resistance value, the reading shifts horizontally and it can be observed that, for the same resistance value, large clock cycle periods correspond to a large number of read operations needed for the sensitization.
This fact can be observed in Fig. 16, where, in the no access region, the voltage level of node SB grows to reach VDD. In order to detect this kind of DRF, it is useful to produce the highest number of consecutive RESs. In fact, a sequence of consecutive RESs produce a good sensitization of the fault by degrading progressively the voltage of one of two core-cell nodes. An easy way to produce long sequence of RESs is the application of a common March test with the addressing order word line after word line.
Fig. 15 Data retention fault caused by high resistive defect Df4 Immediately after the w0 operation, node S is at logic ‘0,’ while node SB is at logic ‘1’ but with a voltage level lower than VDD due to the faulty pull-up of INV1. For the same lack of pull-up, node SB slowly loses the stored charge because of the leakage currents. With the decrease of the voltage of node SB, also INV2 begins to work not perfectly, in particular transistor Mtn2 starts to conduct less than in normal condition while transistor Mtp2 (supposed to be OFF) begins to conduct.